"""
Copyright 2007, Thomas Dejanovic.

This is free software; you can redistribute it and/or modify it
under the terms of the GNU Lesser General Public License as
published by the Free Software Foundation; either version 2.1 of
the License, or (at your option) any later version.

This software is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.

You should have received a copy of the GNU Lesser General Public
License along with this software; if not, write to the Free
Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
02110-1301 USA, or see the FSF site: http://www.fsf.org.
"""

id = "$Id: hatch_target_bus.py 667 2010-07-01 00:12:17Z jayshurtz $"
# $URL: http://hatch.googlecode.com/svn/trunk/hatch/hatch_targets/verilog/obsolete/hatch_target_bus.py $
# $Author: jayshurtz $
version = " ".join(id.split()[1:3])

# TODO - merge this file with hatch_target_bus_verilog.py
# Hatch will automatically connect io ports in a node heirarchy with busses where possible,
# so a physical class of this type is NOT needed.

#from hatch_node_physical import HatchNodePhysical

#class Target_Bus(HatchNodePhysical):
#    """ This is a general target bus class that holds bus type, width,
#        prefix information, etc.  It calls on the relevant code
#        generation modules as required.
#    """

        # TODO - move to verilog generation.
        if False:
            if self.has_property('target'):
                self.set_property('target_bus', hatch_target_bus_verilog.get_target_bus(self))  # build the bus data structure.
                print "building target bus %s in %s"%(self.property('target_bus').name, self.name)

    # TODO - move to verilog generation.
    if False:
        def elaborate (self):
            """ Run any functions needed to flesh out data structures as a prelude to generating anything.
            """
            if self.has_property('target_bus'):
                self.property('target_bus').elaborate() # build the bus data structure.
            else:
                raise AssertionError, "*** ERROR - cant seem to find a target bus definition in %s."%(hatchling.name)



    def __init__(self, hatchling):
        """ """
        if hatchling.property('target') == None:
            raise "*** ERROR - No target bus type specified in hatchling %s."%(hatchling.name)
#        name = hatchling.name + " " + hatchling.property('target')  # Hatchling target property is my name.
#        self.hatchling = hatchling  # XXX Bizarre!

#        HatchNodePhysical.__init__(self, name)

#        # copy the prefix and target from the hatchling for convenience.
#        self.set_property('target', hatchling.property('target'))
#        self.set_property('prefix', hatchling.property('prefix'))

        self.declarationList = []   # XXX What ?
#        self.portList = []


    def add_input_port(self, width, name):
        """ Add an input port required for this bus.  Automaticaly infers an
            internal addition of a wire declration for the port.
        """
        self.portList.append(["input  ", width, name])  # XXX Is this a type ?
        self.add_wire(width, name)
    def add_output_port(self, width, name):
        """ Add an output port required for this bus.  Automaticaly infers an
            internal addition of a wire declration for the port.  Wire
            declarations can be upgraded to registyer declarations as
            required by the particular implementation of a bus.
        """
        self.portList.append(["output ", width, name])
        self.add_wire(width, name)

    def add_wire(self, width, name):
        """ Add a wire declration."""
        self.declarationList.append(["wire", width, name])         
    def add_reg(self, width, name):
        """ Add a register declration."""
        self.declarationList.append(["reg ", width, name])
                                        
    def get_declaration_list(self):
        """ Return a list of ports required to implement the requested target."""
        return self.declarationList
    def get_port_list(self):
        """ Return a list of ports required to implement the target bus."""
        return self.portList

#    def elaborate (self):
#        """ Run any functions needed to flesh out data structures as a
#            prelude to generating anything.
#        """
#        pass
    def write_verilog_setup(self, outputFile):
        """ Write a string with any verilog required to make the target
            bus opperate to the file given.
        """
        outputFile.write(self.verilogSetup)


